Opening for SoC Verification with PCie Gen 5/6 engineer - Bangalore

Job description

Hi, Opening for SoC Verification Engineer with Pcie Gen5/6 experience.Key Responsibilities 10+years of experience:-Execute top-level SoC verification for complex designs integrating PCIe and DDR subsystemsDefine and execute verification strategies, plans, and methodologies for full-chip validationDevelop and maintain UVM/SystemVerilog-based verification environmentsDrive end-to-end verification including integration, performance, and corner-case scenariosEnsure robust coverage through functional, code, and assertion-based verificationDebug and root-cause complex issues across hardware and verification environmentsLead PCIe (Gen 5) and DDR4/DDR5 protocol verification and complianceMentor and guide junior engineers, fostering best practices and technical growth Please share your resume to Regards,Jaya